1. Technical Field
The present invention relates generally to a data transmission system and a data transmission method and, more particularly, to a data transmission system and a data transmission method which transfer information using a Delay Insensitive (DI) data transmission method.
2. Description of the Related Art
With the development of semiconductor processing technology and integrated circuit design technology, a current integrated circuit system is chiefly designed using a System-on-Chip (SoC) method which implements an integrated circuit system in a single chip.
Recently, with the further development of semiconductor processing technology and integrated circuit design technology, there has been a tendency in which the number of elements integrated into a single chip has gradually increased. Accordingly, the wiring structure of transmission wires designed in a single chip is becoming more complicated. Accordingly, if an integrated circuit system is implemented using the SoC design method, the number of transmission wires, the length of the transmission wires, and signal delay due to interference between the transmission wires are design factors that must be significantly taken into consideration to accomplish an appropriate operation of the chip.
Meanwhile, when a synchronous design method using a global clock is applied to an integrated circuit system implemented using the SoC method, there occur clock skew and jitter attributable to an increase in clock speed and the transmission delay of data attributable to an increase in the number of transmission wires and the length of the transmission wires. These problems can be overcome by applying an asynchronous design method to the integrated circuit system implemented using the SoC method.
The asynchronous design method can overcome the above problems of the synchronous design method by performing data transmission based on a DI data transmission method supporting a handshake protocol insensitive to delay time without using a global clock. The asynchronous design method is problematic, however, in that the design of all circuits is complicated and CAD tools for the asynchronous design are insufficient.
Research into a Globally Asynchronous Locally Synchronous (GALS) system has been actively conducted to provide a scheme that is capable of solving the problems of the synchronous design method and the problems of the asynchronous design method at the same time.
The GALS system basically does not use a global clock, and includes a number of LS modules operating in response to independent clocks. Data transmission between the LS modules is performed in compliance with an asynchronous handshake protocol.
As described above, the GALS system solves problems, such as clock skew and jitter, because it does not use a global clock, and secures stable data transmission because data transmission between the LS modules operating with different timing is performed using a DI data transmission method.
In the DI data transmission method, data is represented using an encoding method, such as dual-rail or 1-of-4 encoding method, and a 4-phase handshaking protocol similar to that of the existing synchronous design method is used. However, the 4-phase handshaking protocol must include a space state for informing of data validity not related to data transmission, and the space state has the same latency as data. In a GALS system in which the transmission of data via interconnection extended due to an increased die size is frequent, a 2-phase handshaking protocol method without the space state is more efficient than the 4-phase handshaking protocol method.
Unlike in the existing dual-rail-based 2-phase protocol in which the transmission of data “0” and the transmission of data “1” in two wires are encoded using the state changes of the respective wires, in the dual-rail-based 2-phase handshaking protocol, also known as Level-Encoded 2-phase Dual-Rail (LEDR), the transmission of data “0” is encoded using data in one wire and the transmission of data “1” is encoded using a phase shift in the other wire, and vice versa. That is, the data “0” and the data “1” are encoded as levels, not state changes, in one wire, and pieces of data are distinguished from each other based on a change in the other wire. Consequently, the exclusive-OR (XOR) value of the two wires is changed for each data transmission, and the validity of data is determined by detecting the change. Accordingly, the dual-rail-based 2-phase handshaking protocol has better performance than the existing dual-rail-based 2-phase protocol and can reduce design complexity because data decoding is not required. However, the dual-rail-based 2-phase handshaking protocol is disadvantageous in terms of performance, power consumption, and design complexity corresponding to the number of increased wires because 2N+1 wires are required for the transmission of N-bit data.
Conventional data transmission techniques include a signal transmission technique that is capable of reducing an area occupied by wires by simultaneously sending several different types of signals via one wire between a plurality of functional blocks within an integrated circuit. According to this technique, theoretically, when N-bit data is transmitted, 2^N voltage values in triangular pulse form are encoded and send in one wire, and a reception circuit restores data by detecting the 2^N voltage values. In this case, the overall area of an integrated circuit may be reduced because the number of required wires is reduced. However, the complexity of the reception circuit may be greatly increased because the number of logics that must be decoded increases due to an increase in the number of voltage values that may be encoded in a wire, and thus a decrease in the number of wires is limited. Furthermore, in a multi-valued logic circuit technology using voltage used in the conventional technology, the noise margin characteristic of the voltage may be deteriorated in a receiving circuit because supply voltage within the integrated circuit is gradually lowered. Furthermore, the multi-valued logic circuit technology is unable to be applied to a GALS system because it does not provide a function of supporting a handshake protocol required for DI transmission.
In order to support DI transmission and reduce the number of wires, a protocol using a ternary encoding method is being researched. A data transmission technology using the ternary encoding method is not influenced by the noise margin of the supply voltage because a current mode-type multi-valued logic circuit is used. Furthermore, in this technology, a circuit may be designed using N+1 wires for the transmission of data of N bits because three types of logic states may be represented in one wire.
Furthermore, in order to compensate for a high constant current consumption characteristic occurring in the conventional current mode-type DI data transmission method, research capable of significantly reducing power consumption in a standby state using a new data encoding method had been carried out.
However, the two DI data transmission methods using current mode circuits are disadvantageous in that they may have half of performance, compared to the 2-phase DI data transmission method, such as LEDR, because it is basically based on the 4-phase data transmission method.
In order to compensate for the disadvantage of the DI data transmission methods using current mode circuits, a 2-phase signaling scheme using a current mode DI transmission method was proposed. In this method, in order to compare current input data with next data, an encoder assumes the synchronization between an input request signal and a data signal, a delay device is inserted into the data signal, and delayed current data is extracted from a next input request signal. However, when designing an encoder only under the synchronization assumption that a data signal must be stabilized prior to an input request signal in an asynchronous signal environment, a designer must know the greatest time difference between the input request signal and the data signal and the shortest cycle time of the input request signal in order to determine the delay time of a delay device. This may make it very difficult to determine the delay time of the delay device, or this may mean that the functionality of the encoder cannot be ensured because the desired delay time of the delay device cannot be found in some case (in the case where the greatest time difference between the input request signal and the data signal>the shortest cycle time of the request signal). Furthermore, in the decoder using this technology, a D flip-flop is used in order to restore a data signal, and an additional logic for producing a point of time at which the D flip-flop captures data, that is, the clock signal of the D flip-flop, is required. Furthermore, this technology does not suggest a method of reducing latency in transmission via a long wire, such as the insertion of a buffer, which is commonly used in the transmission of voltage mode binary data.